About JPIET

Department OF Electronics & Communication Engineering

Abhishek Singh

Assistant Professer & HOD

EmailID: abhipra.riya@rediffmail.com

Contact No: 0121-2623009

Education

M.Tech(Signal processing) , B.Tech (Electronics & communication)

Area of Interest

Electrical & Electronics Engineering

Work Experience

10 Years.

Subject Specialization

Analog Integrated Circuit

Subject taught till now

Electrical Engineering, Electronics Engineering, Digital Signal Processing, Signal and Systems, Digital Logic Design, Analog IC’s, Electronic Circuit & Design, Data Communication Network etc.

Workshop / Seminar

1.

Attended one day Workshop on “Rural Development & Management through IT” at JPIET, Meerut in 2012.

2.

Attended two days Workshop on “Recent Development in Optimization Techniques for Solving Industrial Problems” at JPIET, Meerut in 2012.

Academic Achievements

1.

Coordinator, Department of Electronics and Communication at SCRIET, CCS University, Meerut.

2.

Coordinator, Practical Examination at SCRIET, CCS University, Meerut.

3.

Assistant Superintendent of Internal Flying-Squad of Examination 2008 in SCRIET, CCS University, Meerut.

4.

Expert Examiner for the recruitment of Lab-Technician in EC Deptt., SCRIET, CCS University, Meerut.

5.

Member of Anti Ragging Committee (2007-08), SCRIET, CCS University, Meerut.

Honours / Achievements

1.

1st Division with Distinction in M.Tech. (Signal Processing) at AIT Delhi.

2.

GATE Qualified in 2009, 2010, 2011 with Electronics & Communication Stream.

3.

Received Scholarship during M.Tech from MHRD.

Laboratories Development

The work involve collection of data which is required for the laboratories from various leading Institutes of Technology and core Companies of India, on behalf of that preparation of laboratory requirements, verification and recommendation of the items quoted by suppliers and overall supervision of the supply and installation of the equipments. The different laboratories developed are Electronics Engineering and Integrated Circuits.

Projects :

B.Tech Level: Microcontroller based “Electronics Guard for Blind Persons”. Used to detect the obstacles for blind person’s using IR sensors.

M.Tech Level: Mat lab based “Enhancement of Digital Images by using Specified Histogram Techniques.

JP Education trust was established in the year 1993 under the dynamic leadership of Shri Jai Prakash Agarwal and Dr. Hariom Agarwal.

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JPIET Mawana Road
Near Ganga Nagar,
PIN- 250001
Uttar Pradesh, India

Connect With Us

Contact no. 0121-2623009, 0121-2622499 &
0121-2660845
Email: admissions@jpiet.com

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